Tushar Ringe

Tushar Ringe has extensive experience in hardware and ASIC engineering, beginning as a Hardware Engineer at Analog Devices from February 2001 to October 2011, where responsibilities included micro-architecture and RTL coding for SHARC DSP and VMM-based validation for BLACKFIN DSP. Tushar then advanced to Principal Engineer at ARM from January 2015 to July 2021, contributing to various architectures and designing critical components such as chip coherency nodes and memory tagging systems. Following this, Tushar served as CPU Microarchitect at Google from July 2021 to May 2025, focusing on next-generation CPU development, and is currently an ASIC Engineer at Meta since May 2025, working on AI/ML infrastructure. Tushar holds a Master of Technology in Microelectronics & VLSI Design from the Indian Institute of Technology, Madras, and a Bachelor of Engineering in Electronics Engineering from Shri G S Institute of Technology & Science.