Vincent Au

Vincent Au is a seasoned engineering professional with extensive experience in semiconductor technology and design verification. Starting at Cisco Systems, Inc., Vincent contributed to ASIC verification and design for advanced router systems. Following this, a tenure at Ambarella Corporation focused on ASIC design and verification for video codec chips. Vincent then served as a Technical Leader at Violin Memory, enhancing solid-state memory technologies before advancing to a Principal Engineer role at SK hynix memory solutions, developing next-generation storage solutions. At Intel Corporation, Vincent led a global team in the development of FPGAs for diverse markets. Subsequent roles at Cruise involved SOC verification for autonomous vehicles and AI/ML silicon engineering. Currently, Vincent is an ASIC Engineering Manager at Meta, overseeing the deployment of custom ASICs for AI applications across data centers. Vincent holds a Master of Science in Electrical Engineering from Stanford University and a Bachelor's in Electrical Engineering from the University of Waterloo.