Balachandran P is a seasoned RTL Design Engineer with over 8 years of experience in ASIC RTL design, specializing in networking protocols such as 802.3 and SRv6. They have developed expertise in microarchitecture, ECO, and timing closure, and are proficient with various protocols including AMBA and Avalon. Balachandran has a strong background in cross-functional collaboration, working with teams on verification, synthesis, and post-silicon validation. They have been with Microchip Technology Inc. as a Senior Engineer II since 2021 and previously held positions at Cadence Design Systems and HCL Technologies. Balachandran earned a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Mepco Schlenk Engineering College in 2017.
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