Girish P. is a Design Engineer 2 at Microchip Technology Inc. since September 2021, bringing extensive experience in RTL design and verification from previous roles at Celerix Technologies and a startup. At Celerix Technologies, Girish worked as an RTL Design Engineer from August 2018 to December 2020, focusing on high-frequency trading systems utilizing customized market connectivity mechanisms for UDP/TCP connections. Prior to that, a position as an RTL Design and Verification Engineer was held at a startup from January 2021 to September 2021. Girish holds a Bachelor of Engineering degree in Electronics and Communications Engineering from NBN School Of Engineering, completed from 2012 to 2016, and a 10th-grade certificate from Vamanrao Oturkar High School, achieved from 2004 to 2007.
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