Jae Choi is an FPGA IP engineer at Intel Corporation, leveraging over 20 years of design experience in complex ASICs and FPGAs. Jae's past roles include Senior Digital Engineer at Marvell Semiconductor and Digital Design Engineer at Synopsys Inc, where they advanced debug technology for prototyping platforms. Jae has also contributed to the development of ASICs at Cisco Systems and Enphase Energy, focusing on Ethernet and solar power solutions. Currently, Jae is pursuing a Bachelor of Science in Electrical Engineering at the University of Illinois Urbana-Champaign.
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