Jayasree Janapamula is a Technical Staff Engineer at Microchip Technology Inc., specializing in Design for Test, with over 10 years of industrial experience in DFT design and functional verification. Previously, they held positions at AMD, including Senior Design Engineer and Member of Technical Staff, and worked as a Design Engineer I at Soft Machines, focusing on SoC/IP VLSI verification. Jayasree earned a Master of Engineering in Embedded Systems from the Birla Institute of Technology and Science, Pilani, and a Bachelor of Technology in Electronics and Communications Engineering from Sri Vasavi Engineering College.
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