Jonathan Avey

Jonathan Avey is a seasoned PMTS Architect at AMD with over 20 years of experience in digital ASIC design, specializing in high-speed, ultra-low power wireless SoCs and communication architectures. They have held key roles at various companies, including as a Staff Product Design Engineer at PMC-Sierra, where they developed advanced architectures for OTN traffic processing. Jonathan's previous positions include ASIC Design Engineer roles at Ember Corporation and CORETEX Corporation, demonstrating a strong background in project leadership and cross-discipline coordination across global teams. They hold a Bachelor of Science in Computer Science and a degree in Electrical Engineering from Western University.