Lokesh PeddaYenumula

Lokesh PeddaYenumula is a Senior Verification Engineer 1 at Microchip, bringing extensive experience in application-specific integrated circuit engineering within the information technology and services industry. Previously, Lokesh worked as a Design Verification Engineer at PerfectVIPs and Scaledge Technology and served as a VLSI Engineer at Wipro Limited. With a strong foundation in Universal Verification Methodology (UVM), SystemVerilog, and CMOS, Lokesh completed a degree in Electrical, Electronic, and Communications Engineering Technology from Sree Vidyanikethan Engineering College and furthered their education with a course in RTL Design & Verification from Maven Silicon.