Ritesh Singh

Ritesh Singh is a Principal Verification Engineer at Microchip Technology Inc., where they utilize their extensive experience in Verilog, System Verilog, C, and various verification methodologies, including UVM. Ritesh previously worked as a Senior Verification Engineer at Cyient and as an ASIC Engineer at Synaptics, where they specialized in ASIC verification for biometric sensors. Ritesh began their career as an Engineer Trainee at IP Core Solutions and holds an M.Tech in VLSI from Vignan Institute of Technology and Science, as well as a B.Tech in Electronics and Communication from Aurora Scientific Research and Technological Academy.