Sunil Gathani

Sunil Gathani is an experienced engineering professional currently serving as the Digital IP Design Engineering Manager at Microchip Technology Inc. since May 2021, where the focus is on managing Next Generation Advanced High-Speed SerDes PHY IP Design and verification teams. Prior to this, Sunil held the position of Staff ASIC Design Verification Engineer at Intel Corporation from April 2018 to September 2021, leading technical verification for PCIE Gen5. Sunil's career also includes serving as a Senior ASIC Design Verification Engineer at Altera, specializing in High Bandwidth Memory 2.0 verification, and a Senior R&D Verification Design Engineer role at Intel Corporation from June 2007 to February 2015. Sunil holds a Master of Engineering degree in Electrical–Computer and Microelectronic Systems from Universiti Teknologi Malaysia and a Bachelor of Engineering with Honors in Electronics, Laser and Optical Engineering from Multimedia University.