Brian Toronyi is a highly experienced engineer with a strong background in ASIC architecture and micro-architecture design. Currently serving as a Member of Technical Staff ASIC Architect at Micron Technology since January 2020, Brian focuses on hardware accelerators to enhance FTL performance in mNAND and SSD memory controllers. Prior to this role, Brian held various positions, including Micro-Architect Engineer at Intel Corp. and Senior Staff Engineer at Samsung SARC | ACL, where responsibilities included SoC architecture and performance analysis. Additional experience as a Network Engineer at Level 3 Communications and OnFiber Communications, along with a Master’s degree in Circuit Design from The University of Texas at Austin, underscores a diverse skill set and commitment to advancing memory and networking technologies.
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