Jiewei Chen

Jiewei Chen serves as a Principal Engineer in Process Integration at Micron Technology, a position held since April 2019, after progressing from a Sr. Engineer role focused on R&D NAND process integration. As the owner of the 170s 3D RG NAND Staircase Contact Module, and previously the 150s 3D RG NAND Replacement Gate Module, Jiewei has made significant contributions to advancements in NAND technology. Prior experience at Micron includes an internship in wet process non-volatile memory, where fundamental electrochemistry research was conducted to address source corrosion issues. Jiewei holds a Ph.D. in Materials Science and a Master's degree in Statistics from the University of California, Davis, as well as a Bachelor of Engineering in Polymer Materials & Engineering from Zhejiang University, alongside an internship at The Hong Kong University of Science and Technology.