Karthick Chandra is a lead engineer at HCLTech, currently working on memory projects for TSMC’s 3.5 nm nodes. Previously, Karthick served as a physical design engineer at RV-VLSI, handling the Lakshya project, and gained experience at Synopsys Inc., where they managed customer projects utilizing 3 nm and 7 nm technology nodes. Karthick has 1.9 years of experience in ASIC physical design, synthesis, PNR, and STA, and holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Visvesvaraya Technological University.
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