Kunal Parekh

Kunal Parekh is a seasoned semiconductor professional with extensive experience at Micron Technology since March 1992, currently serving as Sr. Director of Technology Development. With a robust background in Advanced Packaging and Interconnects for Semiconductor Memory, Kunal has driven innovation in 3D Memory Architectures, Thermal and Mechanical Modeling, and High Bandwidth Memory (HBM). Previous leadership roles include Senior Director of NAND Process Integration, where Kunal oversaw the development of a novel 3D-NAND architecture, and Director of Advanced Packaging R&D, managing key wafer and package-level processes. Kunal also has experience in Process Integration roles and served on the Technical Committee for the Symposium on VLSI Technology from 2006 to 2010. Kunal holds a Bachelor of Science in Electrical Engineering from the University of Vermont.