Mayuri Katkar

Mayuri Katkar is a Senior AMS Verification Engineer at Micron, where they leverage their knowledge of Cadence tools for analyzing RF and analog circuits and possess expertise in mixed-signal design, particularly PLL analysis across PVT corners. In previous roles at Micron, they advanced from Associate AMS Verification Engineer to Senior AMS Verification Engineer. Mayuri also contributed to the RF design for the SMDP project by MHRD, focusing on the tapeout of a 5mm x 5mm chip. They hold a Master of Technology in VLSI designs from Visvesvaraya National Institute of Technology and a Bachelor of Technology in Electronics and Telecommunication Engineering from Shri Guru Gobind Singhji Institute of Engineering and Technology.