Michael Miller is a Senior Member of Technical Staff in the NVEG Media Architecture Group at Micron Technology, where they have over 28 years of cumulative experience in SSD Media Architecture and memory product development. They have served as Media Architecture Lead for various process nodes, including 2D and 3D NAND, and contributed as the Asynchronous Power Loss Algorithm Architect for client, enterprise, and mobile SSD products. Previously, Michael held roles at Intel Corporation, including CAD Engineer Lead and Product Engineer focused on NOR Flash. They earned a Bachelor of Science in Electronics and Communications Engineering from De La Salle University.
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