Mrinal Mathur

Mrinal Mathur is a Staff Design Verification Engineer with extensive experience in verification methodologies, including UVM and SystemVerilog. They previously served as a Design Verification Engineer at Intel Corporation, where they created test plans and developed test cases for Machine Learning IP. Mrinal has also held positions as a Hardware Engineer at Contec Holdings, where they contributed to FPGA design, and as a Labview Software Programmer at the University of Illinois at Chicago, focusing on resistance and power analysis. Currently, Mrinal is involved in developing a constrained random test-bench for NAND Flash memory at Micron Technology. They hold a Master’s degree in Electrical and Computer Engineering from the University of Illinois at Chicago.