Ramesh Natesh is currently the Director of High Bandwidth Memory (HBM) Design Verification at Micron Technology, a position held since 2024. Previously, Ramesh served as the Director of System-on-Chip (SoC) Discrete Graphics Design Verification at Intel Corporation from 2022 to 2024. Ramesh held several roles at Intel, including Lead for Electrical Validation of Xeon Server CPUs and Engineering Manager for Mixed-Signal IP Pre-Si Verification. Earlier in their career, Ramesh was a Senior Member of Technical Staff at Rambus Inc., focusing on pre-silicon verification and post-silicon validation. Ramesh began their career as an Associate Design Engineer at ST Microelectronics, contributing to various system-on-chip components. Ramesh is currently pursuing education at the University of Pune.
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