Rio Yang

Rio Yang is a Senior Design Verification Engineer currently working at a start-up since September 2023, with prior experience at 美光科技 since April 2020, focusing on PCIE/NVME and CXL verification. Previously, Rio held roles at Avery Design Systems as a Verification IP Solutions Engineer, where responsibilities included developing SystemVerilog based verification IPs for AHCI/SATA, and at Andes Technology Corporation as an Engineer specializing in L1/L2 cache verification. Additional experience includes a position as a Senior ASIC Design Verification Engineer at EpoStar, emphasizing top-level simulation integration and UVM-based verification environments, and a role at 立錡科技 as an Engineer. Rio holds multiple Master's degrees in Computer Science from Chung Yuan Christian University, completed between 2007 and 2013.