Sagar Verma is a Staff Engineer at Micron Technology, where they focus on DEG layout since 2023. With over eight years of experience in analog and mixed signal layout, Sagar has previously contributed to TSMC as a Layout Design Engineer, responsible for developing advanced layouts for memory and AMS projects at 5nm and 7nm processes. Earlier roles included being a Show Programmer and Maintenance Engineer at Vedic Expo, where Sagar oversaw the technical upgrade and maintenance of high-tech exhibits. Sagar holds a degree from Guru Gobind Singh Indraprastha University, awarded in 2011.
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