Yu Wei is a Principal Package Simulation Engineer at Micron Technology, with over a decade of experience in microelectronics, focusing on package warpage control through material and structural optimization. Yu provides crucial design feasibility input during early product development to streamline timelines and employs Engineering and Finite Element Analysis to enhance package design, assembly, technology development, and quality assurance efforts. Previous experience includes R&D engineering at SUMITOMO BAKELITE SINGAPORE PTE. LTD., emphasizing epoxy molding compounds for semiconductor encapsulation and collaboration with customers to develop competitive solutions. Yu holds a Master of Science in Smart Product Design and a Bachelor's degree in Materials Science and Engineering, both from Nanyang Technological University.
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