Basavaraj Patil

Basavaraj Patil is a Senior Silicon Engineer at Microsoft, bringing over nine years of experience in ASIC Design Verification across various IP and subsystem levels. They have developed reusable UVM-based verification environments from scratch and led the verification of complex IPs, including DDR and LPDDR controllers. With expertise in SystemVerilog, UVM, and various protocols, Basavaraj has a strong background in debugging and functional coverage. They previously held positions at Synopsys Inc. and Synapse Design Inc. after starting their career at Aceic Design Technologies. Basavaraj earned a Bachelor of Engineering in Electronics and Communications Engineering from Visvesvaraya Technological University.