Divya Appanna

Divya Appanna is a Principal Firmware Validation Engineer at Microsoft with extensive experience in the semiconductors industry. Previously, Divya held roles at Infosys and Intel Corporation, focusing on low-level design, coding, validation, and post-silicon debug across various projects. Divya earned a Master's degree in VLSI Design from the University of Southern California and a Bachelor's degree in Electronics and Communication from Visvesvaraya Technological University. Skilled in analog design and post-silicon validation of memory and PCIe IPs, Divya demonstrates proficiency in Python scripting, SystemVerilog, and the Cadence Design Suite.