Jaimin Patel

Jaimin Patel is a Senior Design Verification Engineer at Microsoft, currently working on load-store architecture. With over 12 years of experience, Jaimin has held significant roles at companies such as Cadence Design Systems, Samsung SARC, and Qualcomm, focusing on CPU load/store and functional verification. Jaimin's expertise includes designing verification environments, automation scripting, and coverage analysis using tools like System Verilog and UVM. Jaimin earned a Master’s degree in Electrical Engineering from San Jose State University and a Bachelor’s degree in Electronics and Communication from Shri U.V. Patel College of Engineering.