Jonathan George

Jonathan George is a Senior Design Verification Engineer at Microsoft, where they design and maintain methodologies for cluster testbench stimulus. With a decade of experience in design verification, they previously held roles at Hewlett Packard Enterprise and Microsoft, focusing on UVM verification environments and chip testbench development. Jonathan completed a Master’s degree in Computer Engineering at Colorado State University, achieving a 4.0 GPA, and holds a Bachelor’s degree in the same field from Brigham Young University. They began their career with internships at IDEXX Laboratories and ClearCore Electronics LLC, where they honed their skills in software and board design automation.