Michael Ganem is a Senior Hardware Design Engineer at Microsoft, focusing on FPGA logic design for Azure Networking SmartNICs. Prior to this role, they worked at Intel Corporation as an ASIC Digital Design Engineer from 2005 to 2021, gaining extensive experience in PCIe and chip design activities. Earlier in their career, they served as a Hardware Engineer at Elbit Systems Ltd from 2000 to 2005, specializing in the design of digital boards for helmet-mounted systems. Michael holds a DEA in Plasma, Optics, and Electronics from Université de Metz and an Ingenieur degree in Electrical Engineering from CentraleSupélec.
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