Mohit Saini

Mohit Saini is an experienced RTL Design Engineer with a strong foundation in processor microarchitecture and hardware accelerators. Currently at Microsoft, they drive RTL architecture and implementation for next-generation server hardware supporting Azure, with a focus on custom hardware accelerators for data compression, regex engines, and RDMA. Previously, Mohit worked at Qualcomm as a Senior Lead Designer, where they handled RTL design for L2 cache and AXI Bus interfaces. They also have experience as an RTL Designer at Google and as a Systems Engineer at BrahMos Aerospace. Mohit holds a Bachelor’s Degree in Electronics and Communication Engineering from the National Institute of Technology Kurukshetra.