Nijesh c

Nijesh C is a Principal Physical Design Engineer currently working with the Intel GPU team as an RLS SD micro-arch tech lead. They have driven multiple floorplan path finding and RLS Convergence planning projects for GPGPUs and led the first GPGPU Foveros Convergence planning. Nijesh possesses expertise in Foveros Design SD implementation, micro-arch planning, and has a diverse background in various roles within physical design. They earned a Master of Technology in Integrated Circuit Design from the Indian Institute of Technology, Delhi, following their studies at Mahatma Gandhi University.