Hitesh Ahuja

Hitesh Ahuja has over 27 years of experience in the engineering field. From 1993 to 1995, they were a CAD Engineer with Intel Corp, focusing on Test-Tools and developing CAD tools for new test techniques. Hitesh then moved to Extreme Networks as an ASIC Engineer, where they served as a Technical Lead and Manager on a 10/100/1000 MAC chip from 2001 to 2003. In 2007, they joined Arista Networks, Inc. as a Design Engineer, where they were responsible for FPGA design, vendor selection, tool selection, IP selection, and system Verilog verification testbench design. Most recently, they have been the Lead FPGA Engineer at Misapplied Sciences, Inc. since 2020.

Hitesh Ahuja obtained their Bachelor of Technology (B.Tech.) in Electrical Engineering from the Indian Institute of Technology, Delhi between 1987 and 1991. Hitesh then went on to pursue a M.S. in Computer Engineering at the University of Massachusetts Amherst between 1991 and 1993.