Joseph Mously

Joseph Mously is a skilled FPGA Logic Design team leader with extensive experience in both pre and post-silicon validation. Currently, they lead the Logic Design for FPGA based systems at Mobileye while also serving as the Pre/Post Silicon Validation FPGA team leader at Intel Corporation. Previously, from 2001 to 2016, they worked as a Software Engineer at Marvell Israel Ltd., focusing on C++ based projects for SOC systems. Joseph is currently pursuing a degree in Computer Software Engineering at Ort Braude College.