Kandavel R

Kandavel R has over seven years of experience in System on Chip (SOC) and Sub-Chip (Processor) Verification. In 2011, they worked as a Senior Verification Engineer at L&T Infotech in Chennai, India, where they were involved in test case development using C and System Verilog for MMU, Interrupt Controller, CMU, MA, L2-Cache and SRAM modules verification in a Sub-Chip. Kandavel also worked on code, toggle coverage analysis and report generation for Sub-Chip. In 2014, they moved to Mobiveil Inc. in Bangalore, India, where they worked as a Project Lead. Kandavel had around two year experience in Sub-Chip (Processor) Verification and used C based test cases to verify the functionality of other components in the sub-chip. Kandavel also used Tcl based test cases to verify all the modules and memory map in the Backplane Architecture in the chip through SDIO/PCIe host. Prior to that, they worked at Wipro Technologies Ltd in Cochin, India as a Senior Project Engineer for over three years. Kandavel was involved in test case development for multiple modules verification in complex SOC and developed test cases in ARM assembly language for MIBSPI, LIN, HTU and SCI modules in SOC.

Kandavel R completed a Master's degree in VLSI from PSG College of Technology in 2018. Prior to that, they attended PSG College of Technology from 2006-2008. In 2012, they obtained a CCNA certification from Cisco.