Leo Cheng is a Senior Digital Design Verification Engineer at Monolithic Power Systems, Inc., with extensive experience in IP design verification. Prior roles include Senior Design Verification Engineer at Dialog Semiconductor, where responsibilities encompassed OTP, DRM, and WatchDog Timer verification, as well as FLL design verification. Leo Cheng has also held positions as Assistant Manager at SK hynix memory solutions inc., focusing on Unipro verification, and as a Senior Engineer at 立錡科技, specializing in PMIC verification. Earlier experience includes serving as a Principal Engineer at 義隆電子, with expertise in SoC design verification and image processing methodologies. Leo Cheng holds a Master's degree in Telecommunications Engineering from National Chiao Tung University and a Bachelor's degree in Electrical Engineering from National Taipei University of Technology.
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