Deepa Reddy is a Lead Physical Design Engineer at Moschip, having previously served as a Senior Physical Design Engineer at the same company. With expertise in Cadence Tools, Synopsys, and Physical Design implementation, Deepa has experience in Floorplanning, Static Timing Analysis, and Low Power design across various technology nodes including 14nm, 7nm, and 5nm. Deepa holds a Bachelor of Engineering in Electronics and Communications from Malla Reddy Engineering College & Management Sciences and completed a program in VLSI Physical Design at MosChip Academy of Silicon Systems and Technologies.
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