Søren Kragh

Søren Kragh has a strong background in ASIC engineering and design. Søren started their career at LSI Logic in 1996, where they designed peripheral components for embedded 32-bit CPUs. Søren then moved on to MIPS Technologies in 1999, where they designed the central pipeline control of a 64-bit embedded RISC CPU and a 64-bit bolt-on RISC FPU. Søren co-founded Atinec in 2003, where they worked on architectural design and prototyping of a parallel simulation system. In 2004, they joined Enigma Semi ApS as an ASIC Engineer, where they played a key role in designing queue structures for a 40G packet switch fabric chip and developed verification infrastructure. Søren joined Oticon A/S in 2009 as an Engineer and later joined Napatech in 2010 as a Design Engineer.

Søren Kragh completed their education in Electronics at the DTU - Technical University of Denmark. Søren pursued a Master of Science in Electrical Engineering from 1989 to 1994.