Mark Napier

Mark Napier is a seasoned engineering professional with extensive experience in FPGA design and ASIC development. Currently serving as a Principal Engineer - FPGA Designer at Neptune Technology Group since March 2018, Mark focuses on next-generation Software Designed Radio (SDR) products. Previously held roles include Senior Project Engineer at SpaceX, Communication Consultant at Averna, FPGA Design Engineer at STMicroelectronics, and Electrical Engineer at Cisco Systems, where responsibilities included ASIC/IP design, verification, and testing. Mark's career began as a Design Engineer at Geophex and progressed through various positions, culminating in significant contributions to ASIC design and DSP for communications. Mark holds a Master of Science in Electrical Engineering from Mercer University and a Bachelor of Science in Computer Engineering from North Carolina State University.