Brian D. Lee

Brian D. Lee is a seasoned Senior IC Layout Designer currently employed at Neuralink since November 2021. Prior experience includes roles as a Contract Mask Designer at Dolphin Technology, a Contract Layout Designer at Qualcomm, and various contract positions at Oracle, Uniquify Inc., Tabula, Crossbar Inc., and Dolphin Technology. Expertise encompasses the layout of SRAM memory compilers, embedded cache memories, standard cell libraries, and mixed signal logic blocks, utilizing advanced finFET processes. Brian's academic background includes studies at Ohlone College and California State Polytechnic University-Pomona.