Alexander Sotnikov

Alexander Sotnikov is a digital design engineer specializing in custom ASIC design for wireless applications. They completed a Doctor of Philosophy (PhD) in Radioengineering and Telecommunications from Saint Petersburg Electrical Engineering University. Alexander held various engineering roles, including as a Hardware/RTL design engineer at SRI Vector and a Systems Engineer at Quantenna Communications, where they developed reference models for WiFi PHY layer transceiver IPs. Currently, they are a Senior FPGA Engineer at Nokia. Prior to this, Alexander was a Principal Design Engineer at ON Semiconductor, coordinating RTL design and verification activities for critical components of baseband WiFi transceiver chips.