Jignesh Merja

Jignesh Merja is a Senior Manager in ASIC at Nokia, where they currently lead projects in ASIC verification. With extensive experience in ASIC and FPGA verification, Jignesh has worked with various programming languages including Verilog, VHDL, and System Verilog, as well as numerous bus protocols. Jignesh’s previous roles include positions at Infinera as a Principal ASIC Design Engineer, and as a Solution Architect at Arastu Systems. They hold a Bachelor of Engineering degree from Dharmsinh Desai University, completed in 2006.