Leszek Cylupa

Leszek Cylupa is currently an FPGA Verification Lead Engineer at Nokia, a position held since 2020. Previously, they served as a Principal Design Engineer at Cadence Design Systems from 2013 to 2020, where they focused on design specification, verification planning, and developing testing environments. Earlier in their career, Leszek worked as a Front-end ASIC Designer and FAE at Evatronix SA from 2002 to 2013, handling RTL IP core development and customer support. Leszek also pursues event photography with JerBa Studio since 2015. They hold a Master of Science degree in Telecommunications from The Silesian University of Technology, earned in 2001.