Adarsh Mittal

Adarsh Mittal is an experienced ASIC Arch/Design Engineer at NVIDIA since June 2021, contributing to the Coherency Fabric Team by working on protocol specification definitions, address mapping, and network-on-chip architecture and design. Prior to this role, Adarsh served as a Graduate Research Assistant at the University of Wisconsin-Madison, focusing on load-store optimization. Adarsh has a robust background in CPU design and physical design engineering, with achievements including multiple GPU/mobile chip tapeouts. Educational qualifications include a Master’s degree in Computer Science from the University of Wisconsin-Madison and a Bachelor's degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani.