Ashish Hegde

Ashish Hegde is an experienced engineering professional with expertise in ASIC design and verification, currently serving as a Manager and Senior ASIC Designer at NVIDIA since April 2008. Ashish's responsibilities include SOC/full-chip and unit level verification using SystemVerilog (VMM, UVM) and C++, as well as silicon bringup and FPGA-based ASIC prototyping and emulation. Prior to NVIDIA, Ashish worked at Sasken from May 2005 to March 2008 as a Design Engineer, focusing on unit level verification with SystemVerilog and Verilog, and handling RTL coding, synthesis, and equivalence checking. Earlier roles include Software Engineer at LnT Infotech, where device drivers were coded using C, and an internship at Zeta Infotech Pvt Ltd, where Verilog and SystemVerilog test cases were developed for a new simulator. Ashish holds a Bachelor's degree in Electronics and Communications Engineering from Manipal Institute of Technology, complemented by earlier educational qualifications from Mahatma Gandhi Memorial College and Manipal Academy of Higher Education.