Guy Poel is a chip design team leader at NVIDIA, a position they assumed in 2025. Previously, Poel served as a Staff HW Engineer at two companies, including a role as a Senior HW Engineer at Mellanox Technologies from 2016 to 2020. Their educational background includes a BSc in Electrical Engineering from Braude Academic College, completed in 2009, and ongoing internship work in the VLSI lab at the University of Rochester since 2008.
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