Harsh Gupta

Harsh Gupta is a Manager and Senior Physical Design Engineer at NVIDIA, where they are currently focused on Memory-Sub-Systems physical layout for Tegra-SOC designs in 8nm. With a strong foundation in the VLSI industry, Harsh has previously held senior positions at NVIDIA, where they managed teams and coordinated multi-clock interface units in 7nm technology. They began their career with internships at Telecom Centre of Excellence and Tonbo Imaging, gaining valuable experience in telecommunications and FPGA design. Harsh holds a Bachelor of Engineering in Electrical and Electronics Engineering from BITS Pilani - Pilani Campus.