Hemant Patel

Hemant Patel is a seasoned professional in the field of ASIC design engineering, currently serving as a Senior ASIC Design Engineer at NVIDIA since February 2024. Prior experience includes roles as Lead Engineer and Senior Engineer at Qualcomm from June 2019 to February 2024, as well as a Memory Design Engineer at TSMC from August 2016 to June 2019, specializing in SRAM compiler design, characterization, and verification. Possessing over two years of hands-on experience in SRAM circuit design, critical path modeling, memory compiler characterization, design verification, design quality checks, and data verification, Hemant Patel seeks further opportunities in the memory circuit design and verification domain. Hemant Patel holds a Master’s Degree in Electronic Systems from the Indian Institute of Technology, Bombay, obtained in 2016, and a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Maulana Azad National Institute of Technology, completed in 2013.