Jason Yu is a Senior Verification Engineer with 15 years of expertise in SystemVerilog and UVM testbench development, specializing in PCIE Gen5/Gen6 and CXL verification for GPU ASICs. They have 9 years of experience in NAND flash memory verification and possess strong analytical skills for architecture improvement and automation. Jason's professional background includes roles at Micron Technology as a Staff Design Verification Engineer, NVIDIA as a Senior Verification Engineer, and SanDisk, where they led a verification team in full chip verification of NAND flash memory. They hold master’s degrees in Electrical Engineering from both the University of Southern California and National Taiwan University, alongside a bachelor's degree in Mechanical Engineering from National Taiwan University.
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