Joel Yu is a principal chip design engineer with over 15 years of experience specializing in architecture optimization and RTL development. At NVIDIA, they advanced through roles from entry-level design engineer to principal chip design engineer, leading complex digital circuit design and managing cross-functional teams to drive innovation. Prior to that, at Sandia National Laboratories, they focused on digital architecture design and optimization. Currently, Joel is pursuing a master's degree in microelectronics at The University of New Mexico and is also enrolled in a bachelor's degree program in electrical engineering at New Mexico State University.
Location
Santa Clara, United States