Liang Zhou

Liang Zhou is an experienced Principal Engineer and Manager at NVIDIA since February 2015, specializing in CPU architecture and RTL design, with significant contributions including various caches, a return stack buffer, and a formal verification framework. Prior to NVIDIA, Liang Zhou worked as an MTS RTL Design Engineer at AMD, focusing on GPU RTL design, and as an ASIC Engineer 3 at Juniper Networks, specializing in static timing analysis. Liang Zhou began a career in design and verification as an intern at Achronix Semiconductor. Educational credentials include a PhD in Electrical Engineering from the University of Arkansas and a Bachelor of Engineering in Telecommunication Engineering from Hubei University.