Naresh Kamath

Naresh Kamath is a Senior Hardware Engineer at NVIDIA since January 2013, specializing in SOC Emulation, GPU Clocks Verification for Functional and DFT architectures, as well as clocks emulation and bring-up PIC. Previously, Naresh served as a Hardware Intern, developing behavior models for I/Os used on GPU and Tegra SOC, and worked on logic equivalence checking to align behavioral models with SPICE models. Prior experience includes a role as a Project Engineer at Wipro Technologies from July 2010 to July 2011, focusing on VLSI Design and Verification within the wireless division of Texas Instruments. Naresh holds a B.E. in Electronics and Communication Engineering from Manipal Institute of Technology and a Master of Science from the University of Southern California.