PJ

Pavan K J.

Senior DFT Engineer

Pavan K J. is a Senior DFT Engineer at NVIDIA since January 2019, specializing in advanced DFT methodology for GPU and Automobile SOCs, with a focus on architectural enhancements. Previously, Pavan worked as a Graduate Technical Intern at Intel Corporation in 2016, concentrating on Functional Safety (FuSa). Academic experience includes serving as a Graduate Research and Teaching Assistant at Southern Illinois University from August 2013 to December 2018, where responsibilities encompassed teaching VLSI courses. Pavan holds a Ph.D. and a Master’s Degree in Electrical and Computer Engineering from Southern Illinois University, and a Bachelor’s Degree in Electronics and Communication Engineering from Jawaharlal Nehru Technological University. Early education includes high school from Kendriya Vidyalaya, achieving notable academic performance throughout.

Location

Austin, United States

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