游旻倫

旻倫 游 is a Senior ASIC Physical Design Engineer at NVIDIA, where they focus on partition timing enclosure and timing library releases. Previously, they worked as a Physical Design Engineer at CoAsia SEMI Taiwan Ltd., specializing in Samsung 5nm block-level design and various physical verification processes. Earlier in their career, 旻倫 was a Process Integration Engineer at TSMC, where they developed 5G-PMIC NTO and optimized wafer production processes. They hold a Bachelor's degree in Optoelectronic Science and Engineering from National Central University and a Master's degree in Optics from National Taiwan University.